Example Imb Sequences - ARM ARM926EJ-S Technical Reference Manual

9.3

Example IMB sequences

ARM DDI0198D
The following sequence corresponds to steps 1-4 in IMB operation on page 9-3:
clean_loop
MRC p15, 0, r15, c7, c10, 3 ; clean entire dcache using test and clean
BNE clean_loop
MCR p15, 0, r0, c7, c10, 4 ; drain write buffer
STR rx,[ry]
MCR p15, 0, r0, c7, c5, 0
The following sequence illustrates an IMB sequence used after modifying a single
instruction (for example, setting a software breakpoint), with no external
synchronization required:
STR rx,[ry]
MCR p15, 0, ry, c7, c10, 1
MCR p15, 0, r0, c7, c10, 4
MCR p15, 0, ry, c7, c5, 1
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; nonbuffered store to signal L2 world to
; synchronize
; invalidate icache
; store that modifies instruction at address ry
; clean dcache single entry (MVA)
; drain write buffer
; invalidate icache single entry (MVA)
Instruction Memory Barrier
9-5