ARM ARM926EJ-S Technical Reference Manual page 203

ARM DDI0198D
Signal
DRSIZE[3:0]
DRWAIT
DRWBL[3:0]
DRWD[31:0]
INITRAM
IRADDR[17:0]
IRCS
Copyright © 2001-2003 ARM Limited. All rights reserved.
Table A-7 TCM interface signals (continued)
Direction Function
Input Data TCM size.
Static configuration input that specifies the physical
size of TCM memories attached.
0000 = absent
0011 = 4KB
0100 = 8KB
...
1010 = 512KB
1011 = 1MB
Values 0001, 0010, and 1100 to 1111 are reserved.
Input Data TCM wait state input.
If HIGH, the DTCM cannot service the request in
that cycle.
Valid in request cycle and subsequent wait cycles.
Ignored if not a request or wait cycle.
Output Data TCM write data byte lane indicator.
Valid during request cycles.
For reads, set to b0000
For writes indicates which byte(s) are to be written,
depending on the address and the size of the access
(word, halfword, or byte).
Bits of DRWBL are set only when a write is taking
place, so when DnRW is unset all the bits of
DRWBL are also unset.
Output Data TCM write data.
Valid during request cycles when DRnRW is 0.
Valid during waited write cycles.
Input Enables instruction TCM at system reset.
Enables booting from the instruction TCM if
VINITHI is LOW.
Output Instruction TCM address.
This is the word address for the access. Valid during
request cycles.
Output Chip select.
Indicates if an access will take place in the following
cycle. Not valid during wait cycles.
Signal Descriptions
A-15