Figure 5-13 Byte-Banks Of Ram Example - ARM ARM926EJ-S Technical Reference Manual

ARM926EJ-S
DRWD[31:0]
DRADDR[17:0]
DRWBL[3:0]
b0110 DIN[7:0]
DRSIZE[3:0]
CLK
DRWAIT
DRnRW
DRCS
DRRD[31:0]
5.5.3 Multiple banks of RAM example
ARM DDI0198D
The rules for connecting four RAM blocks are:
• Each byte-wide RAM has the same address and chip-select control as the
word-wide RAM.
• The following connections must be made:
— DRWBL[0], DRWD[7:0], and DRRD[7:0], connect to RAM byte 0
— DRWBL[1], DRWD[15:8], and DRRD[15:8], connect to RAM byte 1
— DRWBL[2], DRWD[23:16], and DRRD[23:16], connect to RAM byte 2
— DRWBL[3], DRWD[31:24], and DRRD[31:24], connect to RAM byte 3.
DRWR[7:0]
DRADDR[14:0]
DRWBL[0]
A[14:0] WE DIN[7:0]
CLK CLK
32K RAM
Byte 0
CS DOUT[7:0] CS
DRRD[7:0]
Note
In little-endian mode, DRWBL[0] indicates the LSB of the word and DRWBL[3]
indicates the MSB. In big-endian mode, DRWBL[3] indicates the LSB of the word and
DRWBL[0] indicates the MSB.
If you have to create a large memory out of smaller RAM blocks, there are two methods
for doing this:
• If minimizing power consumption is more important than a fast design, you must
follow the example in Optimizing for power on page 5-22.
Copyright © 2001-2003 ARM Limited. All rights reserved.
DRWR[15:8] DRWR[23:16]
DRWBL[1]
A[14:0] WE DIN[7:0] A[14:0]
CLK
32K RAM 32K RAM
Byte 1 Byte 2
DOUT[7:0] CS
DRRD[15:8]

Figure 5-13 Byte-banks of RAM example

Tightly-Coupled Memory Interface
DRWR[31:24]
DRWBL[2]
WE DIN[7:0] A[14:0]
CLK
32K RAM
Byte 3
DOUT[7:0] CS DOUT[7:0]
DRRD[23:16]
DRWBL[3]
WE
DRRD[31:24]
5-21