Table 3-4 Section Descriptor Bits; Figure 3-6 Coarse Page Table Descriptor - ARM ARM926EJ-S Technical Reference Manual

3.2.5 Coarse page table descriptor
31
ARM DDI0198D
Section descriptor bit assignments are described in Table 3-4.
Bits Description
[31:20] Form the corresponding bits of the physical address for a section
[19:12] Always written as 0
[11:10] The AP bits specify the access permissions for this section
[9] Always written as 0
[8:5] Specify one of the 16 possible domains (held in the domain access control register)
that contain the primary access controls
[4] Should be written as 1, for backwards compatibility
[3:2] These bits (C and B) indicate if the area of memory mapped by this section is
treated as write-back cachable, write-through cachable, noncached buffered, or
noncached nonbuffered
[1:0] These bits must be 10 to indicate a section descriptor
A coarse page table descriptor provides the base address of a page table that contains
second-level descriptors for either large page or small page accesses. Coarse page tables
have 256 entries, splitting the 1MB that the table describes into 4KB blocks. Figure 3-6
shows the format of a coarse page table descriptor.
Coarse page table base address
Note
If a coarse page table descriptor is returned from the first-level fetch, a second-level
fetch is initiated.
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Memory Management Unit

Table 3-4 Section descriptor bits

10 9 8
S
B Domain
Z

Figure 3-6 Coarse page table descriptor

5 4 3 2 1 0
1 SBZ 0 1
3-11