ARM ARM926EJ-S Technical Reference Manual page 17

ARM DDI0198D
Chapter 6 Bus Interface Unit
Read this chapter for a description of the Bus Interface Unit (BIU)
interface to AMBA.
Chapter 7 Noncachable Instruction Fetches
Read this chapter for a description of how speculative noncachable
instruction fetches are used in the ARM926EJ-S processor to improve
performance.
Chapter 8 Coprocessor Interface
Read this chapter for a description of the coprocessor interface. The
chapter includes timing diagrams for coprocessor operations.
Chapter 9 Instruction Memory Barrier
Read this chapter for the Instruction Memory Barrier (IMB) description
and how IMB operations are used to ensure consistency between data and
instruction streams processed by the ARM926EJ-S processor.
Chapter 10 Embedded Trace Macrocell Support
Read this chapter to understand how Embedded Trace Macrocell (ETM)
is supported in the ARM926EJ-S processor.
Chapter 11 Debug Support
Read this chapter for a description of the debug interface and
EmbeddedICE-RT.
Chapter 12 Power Management
Read this chapter for a description of the power management facilities
provided by the ARM926EJ-S processor.
Appendix A Signal Descriptions
This appendix lists the ARM926EJ-S processor signals in functional
groups.
Appendix B CP15 Test and Debug Registers
Read this appendix for detailed information on the registers used for test
and debug.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Preface
xvii