Table 6-1 Supported Hburst Encodings - ARM ARM926EJ-S Technical Reference Manual

Bus Interface Unit
HBURST[2:0] Description
Single Single transfer
Incr4 Four-word incrementing
burst
Incr8 Eight-word incrementing
burst
Wrap8 Eight-word wrapping burst
6-4
Table 6-1 shows the HBURST encodings that the ARM926EJ-S processor uses, and the
operations that perform each burst size.
Operation
Single transfer of word, halfword, or byte:
•
•
•
•
•
Half-line cache write-back. Instruction prefetch, if enabled. Four-word
burst NCNB, NCB, WT, or WB write.
Full line cache write-back. Eight-word burst NCNB, NCB, WT, or WB
write.
Cache linefill.
Note
Incr4 and Incr8 bursts can be aligned to any word boundary.
The ARM926EJ-S processor performs all Thumb instruction fetches as word-wide
transfers on the AHB. See Mapping of level one and level two (AHB) attributes on
page 6-5.
All burst reads and writes are performed by the ARM926EJ-S processor as word-wide
transfers (HSIZE[2:0] = 010). Single reads and writes are performed as byte
(HSIZE[2:0] = 000), halfword (HSIZE[2:0] = 001), or word wide transfers
(HSIZE[2:0] = 010).
Copyright © 2001-2003 ARM Limited. All rights reserved.

Table 6-1 Supported HBURST encodings

data write (NCNB, NCB, WT, or WB that has missed in DCache)
data read (NCNB or NCB)
NC instruction fetch (prefetched and non-prefetched)
page table walk read
continuation of a burst that either lost grant or received a
Split/Retry response.
ARM DDI0198D