Table B-8 Encoding Of The Lockdown Tlb Entry-Select Bit Fields; Figure B-6 Rd Format For Selecting Lockdown Tlb Entry - ARM ARM926EJ-S Technical Reference Manual

31
SBZ
ARM DDI0198D
29 28 26 25
Indexed
entry
Table B-8 describes the entry-select bit fields in the Rd register.

Table B-8 Encoding of the lockdown TLB entry-select bit fields

Bit Name
[31:29] -
[28:26] Indexed entry
[25:0] -
2. Use the following MMU Test Register instructions to access the MVA tag:
MRC p15, 4, <Rd>, c15, c2, 1 ; read lockdown TLB
MCR p15, 4, <Rd>, c15, c3, 1 ; write lockdown TLB
See Figure B-3 on page B-7 for read or write data in the Rd register.
3. Use the following MMU Test Register instructions to read or write the PA and
access permission data:
MRC p15, 4, <Rd>, c15, c4, 1 ; read PA and access permission data
MCR p15, 4, <Rd>, c15, c5, 1 ; write PA and access permission data
See Figure B-4 on page B-8 for the read or write data in the Rd register.
4. Use the following instruction to complete a write to an entry:
MCR p15, 4, <Rd>, c15, c7, 1 ; transfer lockdown storage into RAM
To write an entry into the lockdown TLB, the full sequence is therefore:
MCR p15, 4/5, <Rd>, c15, c3, 1 ; write tag lockdown TLB storage reg
MCR p15, 4/5, <Rd>, c15, c5, 1 ; write PA/PROT lockdown TLB storage reg
MCR p15, 4/5, <Rd>, c15, c7, 1 ; transfer lockdown storage into RAM
To read an entry from the lockdown TLB, the entry must first be written using the above
instructions. The entry can then be read using the following instructions:
MRC p15, 4/5, <Rd>, c15, c2, 1 ; read tag lockdown TLB
MRC p15, 4/5, <Rd>, c15, c4, 1 ; read PA/PROT lockdown TLB
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SBZ

Figure B-6 Rd format for selecting lockdown TLB entry

Definition
Should Be Zero
Indexed entry in lockdown TLB
Should Be Zero
CP15 Test and Debug Registers
0
B-11