ARM ARM926EJ-S Technical Reference Manual page 12

List of Figures
Figure 3-4
Figure 3-5
Figure 3-6
Figure 3-7
Figure 3-8
Figure 3-9
Figure 3-10
Figure 3-11
Figure 3-12
Figure 3-13
Figure 4-1
Figure 4-2
Figure 4-3
Figure 5-1
Figure 5-2
Figure 5-3
Figure 5-4
Figure 5-5
Figure 5-6
Figure 5-7
Figure 5-8
Figure 5-9
Figure 5-10
Figure 5-11
Figure 5-12
Figure 5-13
Figure 5-14
Figure 5-15
Figure 5-16
Figure 5-17
Figure 5-18
Figure 5-19
Figure 6-1
Figure 6-2
Figure 6-3
Figure 8-1
Figure 8-2
Figure 8-3
Figure 8-4
Figure 8-5
Figure 8-6
Figure 8-7
Figure 8-8
Figure 8-9
Figure 8-10
Figure 12-1
xii
First-level descriptor ................................................................................................. 3-9
Section descriptor ................................................................................................... 3-10
Coarse page table descriptor .................................................................................. 3-11
Fine page table descriptor ...................................................................................... 3-12
Section translation .................................................................................................. 3-14
Second-level descriptor .......................................................................................... 3-15
Large page translation from a coarse page table ................................................... 3-17
Small page translation from a coarse page table ................................................... 3-18
Tiny page translation from a fine page table ........................................................... 3-19
Sequence for checking faults .................................................................................. 3-26
Generic virtually indexed virtually addressed cache ................................................. 4-9
ARM926EJ-S cache associativity ........................................................................... 4-10
ARM926EJ-S cache Set/Way/Word format ............................................................ 4-11
Multi-cycle data side TCM access ............................................................................ 5-8
Instruction side zero wait state accesses ................................................................. 5-9
Data side zero wait state accesses ........................................................................ 5-10
Relationship between DRDMAEN, DRDMACS, DRDMAADDR, DRADDR and DRCS ..
5-11
DMA access interaction with normal DTCM accesses ........................................... 5-12
Generating a single wait state for ITCM accesses using IRWAIT .......................... 5-13
State machine for generating a single wait state .................................................... 5-14
Loopback of SEQ to produce a single cycle wait state ........................................... 5-14
Cycle timing of loopback circuit .............................................................................. 5-15
DMA with single wait state for nonsequential accesses ......................................... 5-16
Cycle timing of circuit with DMA and single wait state for nonsequential accesses 5-17
Zero wait state RAM example ................................................................................. 5-20
Byte-banks of RAM example .................................................................................. 5-21
Optimizing for power ............................................................................................... 5-23
Optimizing for speed ............................................................................................... 5-24
TCM subsystem that uses wait states for nonsequential accesses ........................ 5-25
Cycle timing of circuit that uses wait states for non sequential accesses ............... 5-26
TCM subsystem that uses the DMA interface ........................................................ 5-27
TCM test access using BIST .................................................................................. 5-28
Multi-layer AHB system example ............................................................................. 6-8
Multi-AHB system example ...................................................................................... 6-9
AHB clock relationships .......................................................................................... 6-10
Producing a coprocessor clock ................................................................................. 8-2
Coprocessor clocking ............................................................................................... 8-2
LDC/STC cycle timing ............................................................................................... 8-4
MCR/MRC cycle timing ............................................................................................. 8-6
Interlocked MCR ....................................................................................................... 8-7
Latecanceled CDP .................................................................................................... 8-8
Privileged instructions ............................................................................................... 8-9
Busy waiting and interrupts ..................................................................................... 8-10
CPBURST and CPABORT timing ........................................................................... 8-12
Arrangement for connecting two coprocessors ...................................................... 8-14
Deassertion of STANDBYWFI after an IRQ interrupt ............................................. 12-2
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