Miscellaneous Signals - ARM ARM926EJ-S Technical Reference Manual

Signal Descriptions
A.6

Miscellaneous signals

A-10
Table A-5 describes the miscellaneous signals on the ARM926EJ-S processor.
Name Direction
BIGENDINIT Input
CLK Input
CFGBIGEND Output
ARM9EJ-S core
endianness
configuration
EXTEST Input
INTEST Input
nFIQ Input
Not fast interrupt
request
nIRQ Input
Not interrupt
request
SCANENABLE Input
STANDBYWFI Output
Copyright © 2001-2003 ARM Limited. All rights reserved.
Table A-5 Miscellaneous signals
Description
Determines the setting of the B bit in CP15 c1 after a
system reset. When HIGH the reset state of the B bit is 1
(big-endian). When LOW the reset state of the B bit is 0
(little-endian).
This clock times all operations of the ARM926EJ-S
design. All outputs change from the rising edge and all
inputs are sampled on the rising edge. The clock can be
stretched in either phase. Through the use of the
DHCLKEN and IHCLKEN signals, this clock also times
AHB operations. Through the use of the DBGTCKEN
signal, this clock also controls JTAG and debug operations.
This signal reflects the setting of the B bit in CP15 c1.
When HIGH, the processor treats bytes in memory as
being in big-endian format. When LOW, memory is treated
as little-endian.
EXTEST mode test signal. This signal must be LOW
during normal operation.
INTEST mode test signal. This signal must be LOW
during normal operation.
This is the fast interrupt request signal. This signal must be
synchronous to CLK.
This is the interrupt request signal. This signal must be
synchronous to CLK.
Scan enable test signal. This signal must be LOW during
normal operation.
When HIGH indicates that the ARM926EJ-S processor is
in wait for interrupt mode.
ARM DDI0198D