Table 2-12 Effects Of Control Register On Caches - ARM ARM926EJ-S Technical Reference Manual

Cache MMU
ICache disabled Enabled or
disabled
ICache enabled Disabled
ICache enabled Enabled
DCache disabled Enabled or
disabled
DCache enabled Disabled
DCache enabled Enabled
ARM DDI0198D
• the RR bit.
Assuming that TCM regions are disabled, the caches behave as shown in Table 2-12.
Behavior
All instruction fetches are from external memory (AHB).
All instruction fetches are cachable, with no protection checks. All addresses are flat
mapped. That is VA = MVA = PA.
Instruction fetches are cachable or noncachable, and protection checks are performed.
All addresses are remapped from VA to PA, depending on the MMU page table entry.
That is, VA translated to MVA, MVA remapped to PA.
All data accesses are to external memory (AHB).
All data accesses are noncachable nonbufferable. All addresses are flat mapped. That
is VA = MVA = PA.
All data accesses are cachable or noncachable, and protection checks are performed.
All addresses are remapped from VA to PA, depending on the MMU page table entry.
That is, VA translated to MVA, MVA remapped to PA.
If either the DCache or the ICache is disabled, then the contents of that cache are not
accessed. If the cache is subsequently re-enabled, the contents will not have changed.
To guarantee that memory coherency is maintained, the DCache must be cleaned of
dirty data before it is disabled.
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Table 2-12 Effects of Control Register on caches

Programmer's Model
2-15