Figure 5-14 Optimizing For Power - ARM ARM926EJ-S Technical Reference Manual

ARM926EJ-S
ARM DDI0198D
DRWD[31:0]
DRADDR[17:0]
DRWBL[3:0]
DRSIZE[3:0] b1000
DRIDLE
DRSEQ
DRWAIT
DRnRW
DRCS
DRRD[31:0]
Optimizing for speed
Figure 5-15 on page 5-24 shows how to produce a large memory from two smaller
RAM blocks if you are optimizing for speed. Separate write enable control is required
for each RAM block:
WE_bank0 = ~DRADDR[14] & DRnRW
WE_bank1 = DRADDR[14] & DRnRW
No logic is added to the critical DRCS path, but both RAMs are enabled whenever
DRCS is asserted, resulting in higher power consumption.
Copyright © 2001-2003 ARM Limited. All rights reserved.
DRADDR[13:0]
DIN[31:0] BW[3:0]
A[13:0]
RAM 64KB
CLK
DRADDR[14] Bank 1
WE
CS DOUT[31:0]
CLK
Tightly-Coupled Memory Interface
DRADDR[13:0]
DIN[31:0] BW[3:0]
A[13:0]
RAM 64KB
CLK
Bank 0
WE
CS DOUT[31:0]

Figure 5-14 Optimizing for power

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