ARM ARM926EJ-S Technical Reference Manual page 237

Little-endian memory
Load/store architecture
Load Store Unit (LSU)
LSU
Macrocell
Memory bank
Memory coherency
Memory Management Unit (MMU)
Memory Protection Unit (MPU)
Microprocessor
Miss
MMU
ARM DDI0198D
Memory in which:
- a byte or halfword at a word-aligned address is the least significant byte or halfword
within the word at that address
- a byte at a halfword-aligned address is the least significant byte within the halfword at
that address.
See also Big-endian memory.
A processor architecture where data-processing operations only operate on register
contents, not directly on memory contents.
The part of a processor that handles load and store transfers.
See Load Store Unit.
A complex logic block with a defined interface and behavior. A typical VLSI system
comprises several macrocells (such as a processor, an ETM, and a memory block) plus
application-specific logic.
One of two or more parallel divisions of interleaved memory, usually one word wide,
that enable reads and writes of multiple words at a time, rather than single words. All
memory banks are addressed simultaneously and a bank enable or chip select signal
determines which of the banks is accessed for each transfer. Accesses to sequential
word addresses cause accesses to sequential banks. This enables the delays associated
with accessing a bank to occur during the access to its adjacent bank, speeding up
memory transfers.
A memory is coherent if the value read by a data read or instruction fetch is the value
that was most recently written to that location. Memory coherency is made difficult
when there are multiple possible physical locations that are involved, such as a system
that has main memory, a write buffer and a cache.
Hardware that controls caches and access permissions to blocks of memory, and
translates virtual addresses to physical addresses.
Hardware that controls access permissions to blocks of memory. Unlike an MMU, an
MPU does not translate virtual addresses to physical addresses.
See Processor.
See Cache miss.
See Memory Management Unit.
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Glossary
Glossary-13