ARM ARM926EJ-S Technical Reference Manual page 194

Signal Descriptions
A-6
Name
CHSEX[1:0]
Coprocessor
handshake execute
nCPINSTRVALID
Coprocessor valid
instruction
nCPMREQ
Not coprocessor
instruction request
nCPTRANS
Not coprocessor
memory translate
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Table A-2 Coprocessor interface signals (continued)
Direction Description
Input The handshake signals from the Execute stage of the
coprocessors pipeline follower. Indicates ABSENT
(10), WAIT (00), GO (01), or LAST (11). If no
external coprocessors are attached these must be tied
to b10 (ABSENT response).
Output Valid instruction indicator for CPINSTR (replaces
CPTBIT).
Output If this signal is LOW on the rising edge of CLK and
CPCLKEN is HIGH, the instruction on CPINSTR
must enter the coprocessor pipeline.
Output When LOW the coprocessor interface is in a
nonprivileged state. When HIGH the coprocessor
interface is in a privileged state.
ARM DDI0198D