About Embedded Trace Macrocell Support - ARM ARM926EJ-S Technical Reference Manual

Embedded Trace Macrocell Support
10.1

About Embedded Trace Macrocell support

10.1.1 FIFOFULL
10-2
To support real-time trace, the ARM926EJ-S processor provides an interface to enable
connection of an Embedded Trace Macrocell (ETM). For more information on the
ETM, see the ETM9 Technical Reference Manual.
The ETM consists of two parts:
Trace port A trace protocol has been developed to provide a real-time trace
capability for processor cores that are deeply embedded in larger ASIC
designs. Because the ASIC normally includes significant amounts of
on-chip memory, it is not possible to determine how the processor core is
operating by only observing the pins of the ASIC. A trace port is required
to understand the operation of the processor.
Triggering facilities
An extensible specification exists, enabling you to specify the exact set
of trigger resources required for a particular application. Resources
include address and data comparators, counter, and sequencers.
The ETM is used to compress the trace information and export it through a narrow trace
port. An external Trace Port Analyzer (TPA) is used to capture the trace information.
The ARM926EJ-S ETM interface exports the required signals for the ETM to perform
trace. The interface is enabled and disabled by the ETMEN input signal. Where an
ETM module is not required, the ETMEN input can be tied LOW to disable the trace
outputs and save power.
Whenever the ETM FIFO fills up, the ETM asserts its FIFOFULL signal. To prevent
loss in trace coverage, the ARM926EJ-S processor stalls until FIFOFULL is
deasserted.
The ARM926EJ-S processor only stalls on instruction boundaries, to allow any AHB
transfers to complete. Programming of the ETM FIFO watermark must take this into
consideration. If the current instruction is either an
have to accept up to 16 words after FIFOFULL has been asserted.
Interrupts (FIQ or IRQ) prevent the ARM926EJ-S processor from stalling when
FIFOFULL is asserted, unless they are masked. See Test and Debug Register c15 on
page 2-36 for details of how interrupts can be masked during trace.
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or an , then the FIFO might
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