Table B-5 Encoding Of The Tlb Mva Tag Bit Fields; Figure B-3 Rd Format For Accessing Mva Tag Of Main Or Lockdown Tlb Entry - ARM ARM926EJ-S Technical Reference Manual

31
ARM DDI0198D
Bit Name
[30:15] -
[14:10] Indexed entry
[9:0] -
2. Use the following MMU test operation instructions to access the MVA tag:
MRC p15, 4/5, <Rd>, c15, c2, 0 ; read tag in main TLB
MCR p15, 4/5, <Rd>, c15, c3, 0 ; write tag in main TLB
The Rd register contains the read or write data as Figure B-3 shows.
MVA tag

Figure B-3 Rd format for accessing MVA tag of main or lockdown TLB entry

Table B-5 describes the MVA tag access bit fields in the Rd register.
Bit Name
[31:10] MVA tag
[9:5] -
[4] V
[3:0] Size of entry
3. Use the following MMU Test Register instructions to access the PA and access
permission data:
MRC p15, 4/5, <Rd>, c15, c4, 0 ; read PA and access permission data
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Table B-4 Encoding of the main TLB entry-select bit fields
Definition
Should Be Zero.
Indexed entry in main TLB.
Should Be Zero.

Table B-5 Encoding of the TLB MVA tag bit fields

Definition
Modified virtual address.
Should Be Zero.
Valid bit.
Size of entry:
b1011 = 1MB section
b0111 = 64KB page
b0101 = 16KB subpage of 64KB page
b0011 = 4KB page
b0001 = 1KB page or 1KB subpage of 4KB page.
CP15 Test and Debug Registers
10 9 5 4 3
Size of
SBZ V
entry
0
B-7