Table 2-9 Line Length Encoding; Table 2-10 Example Cache Type Register Format - ARM ARM926EJ-S Technical Reference Manual

ARM DDI0198D
The line length of the cache is determined by the Len field. The Len field is bits [13:12]
for the DCache and bits [1:0] for the ICache. Table 2-9 shows the line length encoding.
The cache type register values for an ARM926EJ-S processor with the following
configuration are shown in Table 2-10:
• separate instruction and data caches
• DCache size = 8KB, ICache size = 16KB
• associativity = 4-way
• line length = eight words
• caches use write-back, register 7 for cache cleaning, and Format C for cache
lockdown.
See Cache Lockdown Register c9 on page 2-26 for more details on Format C for cache
lockdown.
Function
Reserved
Ctype
S
Dsize Reserved
Size
Assoc
M
Len
Copyright © 2001-2003 ARM Limited. All rights reserved.

Table 2-10 Example Cache Type Register format

Register bits Value
[31:29] b000
[28:25] b1110
[24] b1 = Harvard cache
[23:22] b00
[21:18] b0100 = 8KB
[17:15] b010 = 4-way
[14] b0
[13:12] b10 = 8 words per line (32 bytes)
Programmer's Model

Table 2-9 Line length encoding

Len field Cache line length
b10 8 words (32 bytes)
Other values Reserved
2-11