Using Synchronous Sram As Tcm Memory - ARM ARM926EJ-S Technical Reference Manual

5.8

Using synchronous SRAM as TCM memory

ARM DDI0198D
If you use SRAM to implement TCM memory, then your library RAM must meet the
following requirements:
• It must be synchronous. All timings must be relative to the rising clock edge.
• It must have a chip select (RAM enable).
• The RAM outputs must always be valid. They must not be tristated.
• Byte write control is required.
• RAM setup times must be less than 10-15% and access times must be less than
40-50% of the target cycle time. Violation of these requirements results in a
slower design. Setup and access times can be balanced by skewing the clock to
the RAM.
Ideally each TCM can be constructed from single RAM blocks. However, this is not
always possible for the following reasons:
• If your RAM does not have byte write control, you must construct the word-wide
RAM out of four byte-wide RAMs. See Producing byte writable memory using
word writable RAM on page 5-20.
• If your compiler cannot produce a single RAM block that is the required size, or
if a single RAM block does not meet the timing requirements. In these cases, you
must produce the RAM out of two or more blocks of smaller RAM. See Multiple
banks of RAM example on page 5-21.
Ideally, your RAM block can connect directly to the ARM926EJ-S TCM interface.
However, this is not always possible, and additional logic is required in the following
cases:
• All TCM signals are driven as active HIGH. If your RAM requires active LOW
signals, you must add inverters to create the active LOW signals.
• If power control logic is required.
• If a RAM is non single-cycle, or hardware DMA arbitration is required, logic is
required to drive the appropriate wait signal.
Note
DRADDR is always a word address. DRWBL is used as a byte lane strobe to select the
appropriate byte of the addressed word on writes. Reads are always word-wide.
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Tightly-Coupled Memory Interface
5-31