Table 2-16 Fsr Status Field Encoding - ARM ARM926EJ-S Technical Reference Manual

Programmer's Model
2.3.7 Fault Address Register c6
2.3.8 Cache Operations Register c7
2-20
Table 2-16 shows the encodings used for the status field in the FSR, and if the Domain
field contains valid information. See Fault address and fault status registers on
page 3-21 for details of MMU aborts.
Priority Source
Highest Alignment
External abort on translation
Translation
Domain
Permission
Lowest External abort
Register c6 accesses the Fault Address Register (FAR). The FAR contains the Modified
Virtual Address of the access being attempted when a Data Abort occurred. The FAR is
only updated for Data Aborts, not for Prefetch Aborts. The FAR is updated for
alignment faults, and external aborts that occur while the MMU is disabled.
You can use the following instructions to access the FAR:
MRC p15, 0, <Rd>, c6, c0, 0 ; read FAR
MCR p15, 0, <Rd>, c6, c0, 0 ; write FAR
Writing c6 sets the FAR to the value of the data written. This is useful for a debugger to
restore the value of the FAR to a previous state.
The CRm and Opcode_2 fields Should Be Zero when reading or writing CP15 c6.
Register c7 controls the caches and the write buffer. The function of each cache
operation is selected by the Opcode_2 and CRm fields in the MCR instruction used to
write to CP15 c7. Writing other Opcode_2 or CRm values is Unpredictable.
Copyright © 2001-2003 ARM Limited. All rights reserved.

Table 2-16 FSR status field encoding

Size Status
- b00x1
First level b1100
Second level b1110
Section b0101
Page b0111
Section b1001
Page b1011
Section b1101
Page b1111
Section or page b10x0
Domain
Invalid
Invalid
Valid
Invalid
Valid
Valid
Valid
Valid
Valid
Invalid
ARM DDI0198D