About The Mmu - ARM ARM926EJ-S Technical Reference Manual

Memory Management Unit
3.1

About the MMU

3-2
The ARM926EJ-S MMU is an ARM architecture v5 MMU. It provides virtual memory
features required by systems operating on platforms such as Symbian OS, WindowsCE,
and Linux. A single set of two-level page tables stored in main memory is used to
control the address translation, permission checks, and memory region attributes for
both data and instruction accesses.
The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the
information held in the page tables.
To support both sections and pages, there are two levels of address translation. The
MMU puts the translated physical addresses into the MMU Translation Lookaside
Buffer TLB.
The MMU TLB has two parts:
• the main TLB
• the lockdown TLB.
The main TLB is a two-way, set-associative cache for page table information. It has 32
entries per way for a total of 64 entries. The lockdown TLB is an eight-entry
fully-associative cache that contains locked TLB entries. Locking TLB entries can
ensure that a memory access to a given region never incurs the penalty of a page table
walk. For more details of the TLBs see TLB structure on page 3-31.
The MMU features are:
• standard ARM architecture v4 and v5 MMU mapping sizes, domains, and access
protection scheme
• mapping sizes are 1MB (sections), 64KB (large pages), 4KB (small pages), and
1KB (tiny pages)
• access permissions for large pages and small pages can be specified separately for
each quarter of the page (subpage permissions)
• hardware page table walks
• invalidate entire TLB using CP15 c8
• invalidate TLB entry selected by MVA, using CP15 c8
• lockdown of TLB entries using CP15 c10.
The following subsections are:
• Access permissions and domains on page 3-3
• Translated entries on page 3-3
• MMU program accessible registers on page 3-4
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