ARM ARM926EJ-S Technical Reference Manual page 183

Table of Contents

ARM DDI0198D

To perform an access using scan chain 15, you must:

During the SHIFT-DR state of the TAP state machine, shift in the read/write bit,

operations the data value field does not have to be written.

Move through UPDATE-DR. The operation specified by the register address and

write not read bits does not start.

Return to SHIFT-DR and perform a shift operation so that bits 32, and [31:0] are

read, and a NOP instruction (bit 32 = 0) is shifted in.

Move through UPDATE-DR. No operation is performed because bit 32 is 0.

Check the access complete value that is shifted out. If it is 1, the operation has

completed and bits [31:0] contain valid data for reads. If it is 0, the access has not

completed and you must go back to step 3.

Note

If Multi-ICE is used, then this has the restriction that a maximum of 40 bits of any scan

chain can be written at a time. Because scan chain 15 is 48 bits long, CP15 register

writes require two operations to write all the required bits, and initiate the access. This

can be done by first writing bits [31:0] with the required data value, and bit 32 to 0. This

has the effect of presetting the data value field for the next operation. The second

operation sets bits [47:33] to the required values, and bit 32 to 1 to initiate the access.

This relies on the specific behavior of scan chain 15, which enables data to be

recirculated if a value is scanned in with bit 32 set to 0, and there is no pending access.

In this case the transition through UPDATE-DR does not modify the contents of the

scan chain, and the value written in can safely be read back out in a subsequent

CAPTURE-DR, SHIFT-DR sequence.

The mapping of scan chain 15 to CP15 registers is done in the same way as a CP15

MRC/MCR operation. Bits [46:33] of the scan chain are mapped onto Opcode_1,

Opcode_2, CRn, and CRm.

Debug Support

11-3

Table of Contents

Show Quick Links

Table of Contents