Debug Signals; Table A-3 Debug Signals - ARM ARM926EJ-S Technical Reference Manual

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Debug signals

ARM DDI0198D
Table A-3 describes the ARM926EJ-S processor debug signals.
Name
COMMRX
Communications
channel receive
COMMTX
Communications
channel transmit
DBGACK
Debug acknowledge
DBGDEWPT
Data watchpoint
DBGEN
Debug enable
DBGEXT[1:0]
EmbeddedICE-RT
external input
DBGIEBKPT
Instruction breakpoint
DBGINSTREXEC
Instruction executed
Copyright © 2001-2003 ARM Limited. All rights reserved.
Direction Description
Output When HIGH, this signal denotes that the comms
channel receive buffer contains valid data waiting to
be read.
Output When HIGH, this signal denotes that the comms
channel transmit buffer is empty.
Output When HIGH indicates that the processor is in debug
state.
Input Asserted by external hardware to halt execution of
the processor for debug purposes. If HIGH at the end
of a data memory request cycle, it causes the
ARM926EJ-S processor to enter debug state.
Input Enables the debug features of the processor. This
signal must be tied LOW if debug is not required.
Input Inputs to the EmbeddedICE-RT logic that enable
breakpoints or watchpoints to be dependent on
external conditions.
Input Asserted by external hardware to halt execution of
the processor for debug purposes. If HIGH at the end
of an instruction fetch, it causes the ARM926EJ-S
processor to enter debug state if that instruction
reaches the Execute stage of the processor pipeline.
Output Indicates that the instruction in the Execute stage of
the processor pipeline has been executed.
Signal Descriptions

Table A-3 Debug signals

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