Jtag Signals - ARM ARM926EJ-S Technical Reference Manual

A.5

JTAG signals

ARM DDI0198D
Table A-4 describes the ARM926EJ-S processor JTAG signals.
Name
DBGIR[3:0]
TAP controller
instruction register
DBGnTRST
Not test reset
DBGnTDOEN
Not DBGTDO enable
DBGSCREG[4:0]
DBGSDIN
External scan chain
serial input data
DBGSDOUT
External scan chain
serial data output
DBGTAPSM[3:0]
TAP controller state
machine
DBGTCKEN
DBGTDI
DBGTDO
DBGTMS
Copyright © 2001-2003 ARM Limited. All rights reserved.
Direction Description
Output These four bits reflect the current instruction loaded
into the TAP controller instruction register. These bits
change when the TAP controller is in the
UPDATE-IR state.
Input This is the active LOW reset signal for the
EmbeddedICE-RT internal state. This signal is a
level-sensitive asynchronous reset input.
Output When LOW, indicates that the serial data is being
driven out of the DBGTDO output. Normally used as
an output enable for a DBGTDO pin in a packaged
part.
Output These five bits reflect the ID number of the scan chain
currently selected by the TAP controller. These bits
change when the TAP controller is in the
UPDATE-DR state.
Output Contains the serial data to be applied to an external
scan chain.
Input Contains the serial data out of an external scan chain.
When an external scan chain is not connected, this
signal must be tied LOW.
Output This bus reflects the current state of the TAP
controller state machine.
Input Synchronous test clock enable.
Input Test data input for debug logic.
Output Test data output from debug logic.
Input Test mode select for TAP controller.
Signal Descriptions
Table A-4 JTAG signals
A-9