ARM ARM926EJ-S Technical Reference Manual page 210

CP15 Test and Debug Registers
B.1.2 Debug and Test Address Register
B-4
Bit 15, disable block-level clock gating
You can use this bit to disable block-level clock gating with the
ARM926EJ-S processor. This bit does not affect the functionality of the
ARM926EJ-S processor. It allows the benefits of block-level clock gating
to be evaluated without the requirement to build two different
implementations of the ARM926EJ-S macrocell, one with block-level
clock gating, one without.
Bit 16, disable NC instruction prefetching
You can use this bit to disable speculative prefetching for instructions in
noncachable areas of memory. The default behavior of ARM926EJ-S
processor is to perform speculative sequential instruction fetches on the
AHB interface. Disabling prefetching prevents any speculative
noncachable instruction prefetches by the ARM926EJ-S memory
system, and only instruction requests issued by the ARM9EJ-S core
result in instruction fetches on the AHB interface.
Bits 17 & 18, abort instruction TLB miss
You can use the abort data TLB miss and abort instruction TLB miss bits
to prevent page table walks occurring as the result of a TLB miss. When
set, a TLB miss results in the access being aborted as if the access has
resulted in a translation fault, and a value of
status field of the appropriate FSR.
Bit 19, test and clean all
You can use the test-and-clean-all bit to modify the behavior of the test
and clean, and test clean and invalidate instructions so that a single
instruction can be used to clean or clean and invalidate the entire cache.
This is only intended for use by a debugger, to provide an efficient way
to clean the data cache using scan chain 15.
This register defines the address used for debug and test operations, and for MMU test
operations using the MMU Test Register.
You can access the Debug and Test Address Register using the following instructions:
MRC{cond} p15,0,<Rd>,c15,c1,0 ; Read Debug and Test Address Register
MCR{cond} p15,0,<Rd>,c15,c1,0 ; Write Debug and Test Address Register
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