Figure 5-11 Cycle Timing Of Circuit With Dma And Single Wait State For Nonsequential Accesses - ARM ARM926EJ-S Technical Reference Manual

T1
CLK
DRCS
DRSEQ
DRADDR A
DRWAIT
DMAWAIT
FORCE_NSEQ
REQCLK
CS
A B
SEQ
RD
DRRD

Figure 5-11 Cycle timing of circuit with DMA and single wait state for nonsequential accesses

ARM DDI0198D
T2 T3 T4
A
D(B)
In cycle T1, the ARM926EJ-S initiates a sequential request to address A and the DMA
gains ownership of the TCM. DRWAIT is asserted because of DMAWAIT. The CS, A,
WE signals for the TCM are sourced from the DMA. The values of DRADDR,
DRBWL and DnRW are registered.
In cycle T2, the DMA access is still active (two cycle nonsequential access). DRWAIT
is held HIGH because of DMAWAIT.
In cycle T3, the DMA access completes and DMAWAIT is deasserted. The access
attributes captured at the end of T1 are used to generate the CS, A and WE signals for
the TCM. DRWAIT is asserted because of FORCE_NSEQ.
In cycle T4, FORCE_NSEQ is deasserted causing DRWAIT to be deasserted
indicating that the access will complete in the next cycle.
Copyright © 2001-2003 ARM Limited. All rights reserved.
T5 T6 T7
A+1 A+2
A+1 A+2 C
D(A)
D(A+1) D(A+2)
D(A)
D(A+1) D(A+2)
Tightly-Coupled Memory Interface
T8 T9 T10
D
D
D(C)
T11
D(D)
D(D)
5-17