Figure 4-3 Arm926Ej-S Cache Set/Way/Word Format - ARM ARM926EJ-S Technical Reference Manual

32-A
31
Way
ARM DDI0198D
• the ARM926EJ-S caches are four-way Associative
• the range of tags addressed by the Index define a Way
• the number of tags in a Way is the number of Sets, NSETS.
The Set/Way/Word format for ARM926EJ-S caches is shown in Figure 4-3.
31-A
In Figure 4-3:
A = log Associativity.
2
For example, for a four-way cache A = 2.
S = log NSETS.
2
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SBZ

Figure 4-3 ARM926EJ-S cache Set/Way/Word format

Caches and Write Buffer
S+5 S+4 5 4 2 1 0
Set select
Word
(= Index)
SBZ
4-11