Mmu Faults And Cpu Aborts - ARM ARM926EJ-S Technical Reference Manual

3.3

MMU faults and CPU aborts

3.3.1 Fault address and fault status registers
ARM DDI0198D
The MMU generates an abort on the following types of faults:
• alignment faults (data accesses only)
• translation faults
• domain faults
• permission faults.
In addition, an external abort can be raised by the external system. This can happen only
for access types that have the core synchronized to the external system:
• page walks
• noncached reads
• nonbuffered writes
• noncached read-lock-write sequence (SWP).
Alignment fault checking is enabled by the A bit in CP15 c1. Alignment fault checking
is not affected by whether or not the MMU is enabled. Translation, domain, and
permission faults are only generated when the MMU is enabled.
The access control mechanisms of the MMU detect the conditions that produce these
faults. If a fault is detected as a result of a memory access, the MMU aborts the access
and signals the fault condition to the CPU core. The MMU retains status and address
information about faults generated by the data accesses in the data fault status register
and fault address register (see Fault address and fault status registers).
The MMU also retains status about faults generated by instruction fetches in the
instruction fault status register.
Note
The address information for an instruction side abort is contained in the core link
register r14_abt.
An access violation for a given memory access inhibits any corresponding external
access to the AHB interface, with an abort returned to the CPU core.
On a Data Abort, the MMU places an encoded four-bit value, the fault status, along with
the four-bit encoded domain number, in the data FSR. Similarly, on a Prefetch Abort, in
the instruction FSR (intended for debug purposes only). In addition, the MVA
associated with the Data Abort is latched into the FAR. If an access violation
simultaneously generates more than one source of abort, they are encoded in the priority
given in Table 3-9. The FAR is not updated by faults caused by instruction prefetches.
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Memory Management Unit
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