List Of Tables - ARM ARM926EJ-S Technical Reference Manual

List of Tables

ARM926EJ-S Technical Reference Manual
Table 2-1
Table 2-2
Table 2-3
Table 2-4
Table 2-5
Table 2-6
Table 2-7
Table 2-8
Table 2-9
Table 2-10
Table 2-11
Table 2-12
Table 2-13
Table 2-14
Table 2-15
Table 2-16
Table 2-17
Table 2-18
Table 2-19
Table 2-20
Table 2-21
Table 2-22
ARM DDI0198D
Change history .............................................................................................................. ii
CP15 register summary ............................................................................................ 2-3
Address types in ARM926EJ-S ................................................................................. 2-4
CP15 abbreviations ................................................................................................... 2-5
Reading from register c0 ........................................................................................... 2-7
Register 0, ID code ................................................................................................... 2-8
Ctype encoding ......................................................................................................... 2-9
Cache size encoding (M=0) .................................................................................... 2-10
Cache associativity encoding (M=0) ....................................................................... 2-10
Line length encoding ............................................................................................... 2-11
Example Cache Type Register format .................................................................... 2-11
Control bit functions register c1 ............................................................................... 2-13
Effects of Control Register on caches ..................................................................... 2-15
Effects of Control Register on TCM interface .......................................................... 2-16
Domain access control defines ............................................................................... 2-18
FSR bit field descriptions ........................................................................................ 2-19
FSR status field encoding ....................................................................................... 2-20
Function descriptions register c7 ............................................................................ 2-21
Cache operations c7 ............................................................................................... 2-22
Register c8 TLB operations ..................................................................................... 2-25
Cache Lockdown Register instructions ................................................................... 2-27
Cache Lockdown Register L bits ............................................................................. 2-28
TCM Region Register instructions .......................................................................... 2-29
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