Figure 1-2 Arm926Ej-S Interface Diagram (Part One) - ARM ARM926EJ-S Technical Reference Manual

Introduction
Clock
Interrupts
Miscellaneous
configuration
JTAG debug
Debug
1-4
CLK
nFIQ
nIRQ
STANDBYWFI
BIGENDINIT
VINITHI
CFGBIGEND
TAPID[31:0]
COMMRX
COMMTX
DBGACK
DBGEN
DBGRQI
ARM926EJ-S
EDBGRQ
DBGEXT[1:0]
DBGINSTREXEC
DBGRNG[1:0]
DBGIEBRKPT
DBGDEWPT
DBGnTRST
DBGTCKEN
DBGTDI
DBGTMS
DBGTDO
DBGIR[3:0]
DBGSCREG[4:0]
DBGTAPSM[3:0]
DBGnTDOEN
DBGSDIN
DBGSDOUT
Copyright © 2001-2003 ARM Limited. All rights reserved.
DRDMAEN
DRDMAADDR[17:0]
DRDMACS
DRnRW
DRADDR[17:0]
DRWR[31:0]
DRIDLE
DRCS
DRWBL[3:0]
DRSEQ
DRRD[31:0]
DRWAIT
DRSIZE[3:0]
IRDMAEN
IRDMAADDR[17:0]
IRDMACS
IRnRW
IRADDR[17:0]
IRWR[31:0]
IRIDLE
IRCS
IRWBL[3:0]
IRSEQ
IRRD[31:0]
IRWAIT
IRSIZE[3:0]
DHADDR[31:0]
DHBL[3:0]
DHBURST[2:0]
DHBUSREQ
DHCLKEN
DHGRANT
DHLOCK
DHPROT[3:0]
DHRDATA[31:0]
DHREADY
DHRESP[1:0]
DHSIZE[2:0]
DHTRANS[1:0]
DHWDATA[31:0]
DHWRITE

Figure 1-2 ARM926EJ-S interface diagram (part one)

Data
memory
interface
Instruction
memory interface
Data
AHB
ARM DDI0198D