ARM ARM926EJ-S Technical Reference Manual page 245

Index
The items in this index are listed in alphabetical order. The references given are to page numbers.
A
A bit 2-14
Aborts, external 3-29
Access control, domain 3-24
Access permission bits 3-24
Access permissions 3-3
Access priorities, TCM and cache 4-8
Address alignment 6-6
Address translation 3-5
Addresses 2-4
AHB
clocking 6-10
signals A-3
system considerations 6-6
transfers 6-3
Alignment fault 3-27
enable/disable 2-14
ARM926EJ-S
block diagram 1-2
interfaces 1-3
programmer's model 2-2
ARM DDI0198D
Assoc field 2-10
B
Block diagram 1-2
Bus interface unit 6-2
Busy-waiting 8-10
Byte accesses 6-6
Byte lane indication 6-6
Byte writable memory 5-20
C
C and B bits
DCache 4-6
write-through (WT) 4-2
C bit 2-14
settings, ICache 4-5
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Cache
access priorities 4-8
associativity encoding 2-10
debug control register B-12
enabling 4-5
features 4-2
lockdown regsiter 2-26
operations 2-21
operations register 2-21
RAMs 12-3
size encoding 2-10
type 2-9
type register 2-7, 2-8
type register example format 2-11
unlock procedure 2-29
way format 4-9
way, loading addresses 2-28
writeback (WB) 4-2
write-through (WT) 4-2
CDP instructions 8-8
Clean and invalidate single data entry
2-21
Clean single data entry 2-21
Index-1