ARM ARM926EJ-S Technical Reference Manual page 188

Power Management
12-4
MMU RAMs
The RAM used to implement the MMU can be safely powered down if the MMU has
been disabled (using CP15 control register c1) and it contains no valid entries.While the
MMU is disabled, only explicit CP15 operations can cause the MMU RAM to be
accessed (c8 TLB maintenance operations, and c15 MMU test/debug operations).
These instructions must not be executed while the MMU RAM is powered down.The
MMU RAM must be powered up prior to re-enabling the MMU.
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