Figure 5-15 Optimizing For Speed - ARM ARM926EJ-S Technical Reference Manual

Tightly-Coupled Memory Interface
5.5.4 Sequential ROM example
5-24
ARM926EJ-S
DRWD[31:0]
DRADDR[17:0]
DRWBL[3:0]
DRnRW
DRADDR[14]
DRSIZE[3:0] b1000
DRSEQ
DRWAIT
DRCS
DRRD[31:0]
The diagram in Figure 5-16 on page 5-25 shows an example of a TCM sub-system that
uses wait states for nonsequential accesses. The ROM used to hold instructions can
cycle at the same frequency as the ARM926EJ-S processor it is interfaced to. However,
the memory access time for the ROM (time from chip-select/address to data out) is not
fast enough to be directly interfaced to the ARM926EJ-S processor.
Copyright © 2001-2003 ARM Limited. All rights reserved.
DRADDR[14]
DIN[31:0] BW[3:0]
A[13:0]
RAM 64KB
WE
CLK
Bank 1
CS DOUT[31:0]
CLK

Figure 5-15 Optimizing for speed

DRWD[31:0]
DRADDR[13:0]
DRWBL[3:0]
DIN[31:0] BW[3:0]
A[13:0]
RAM 64KB
WE
CLK
Bank 0
CS DOUT[31:0]
ARM DDI0198D