Figure B-10 Memory Region Attribute Resolution - ARM ARM926EJ-S Technical Reference Manual

ARM DDI0198D
Figure B-10 shows the flow and precedence of CP15 c15 control bits in resolving the
cachable and bufferable attributes of a memory reference.
NCNB
NCB
MMU
CNB (write-through)
CB (write-back)
MDDEB bit:
MMU disabled,
DCache enabled
C and B bits
M, C, and I bits
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Memory
region
remapping
Memory Region Remap Register
Debug Override Register
Page table descriptor
Control Register

Figure B-10 Memory region attribute resolution

CP15 Test and Debug Registers
NCNB
NCB
NCB store
CNB (write-through)
CB (write-back)
FNCB bit:
Force NCB store
to be NCNB
Force
to be
NCNB
B-17