Table B-6 Encoding Of The Tlb Entry Pa And Ap Bit Fields; Figure B-4 Rd Format For Accessing Pa And Ap Data Of Main Or Lockdown Tlb Entry - ARM ARM926EJ-S Technical Reference Manual

CP15 Test and Debug Registers
31
B-8
MCR p15, 4/5, <Rd>, c15, c5, 0 ; write PA and access permission data
The Rd register contains the read or write data as shown in Figure B-4.

Figure B-4 Rd format for accessing PA and AP data of main or lockdown TLB entry

Table B-6 describes the PA and access permission bit fields in the Rd register.
Bit Name
[31:10] PA
[9:8] -
[7:4] Domain select
[3:2] AP
[1] C
[0] B
4. Use the following instruction to complete a write to an entry:
MCR p15, 4/5, Rd, c15, c7, 0 ; transfer main storage into RAM
To write an entry into the 2-way main TLB, the full sequence is therefore:
MCR p15, 4/5, <Rd>, c15, c3, 0 ; write tag main TLB storage reg
MCR p15, 4/5, <Rd>, c15, c5, 0 ; write PA/PROT main TLB storage reg
MCR p15, 4/5, <Rd>, c15, c7, 0 ; transfer main storage into RAM
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PA

Table B-6 Encoding of the TLB entry PA and AP bit fields

Definition
Physical address.
Should Be Zero.
Domain select:
b0000 = D0
b0001 = D1
.
.
.
b1110 = D14
b1111 = D15.
Access permission:
b00 = No access.
b01 = Privileged, read/write. User, no access.
b10 = Privileged, read/write. User read-only.
b11 = Privileged, read/write. User, read/write.
Cachable bit.
Bufferable bit.
10 9 8 7 4 3
Domain AP
SBZ
select [1:0]
ARM DDI0198D
2 1 0
C B