Figure 8-5 Interlocked Mcr - ARM ARM926EJ-S Technical Reference Manual

8.3.1 Interlocked MCR
Coprocessor pipeline
CLK
CPINSTR[31:0]
nCPMREQ
CPPASS
CPLATECANCEL
CHSDE[1:0]
CHSEX[1:0]
CPDOUT[31:0]
MCR
CPDIN[31:0]
MRC
ARM DDI0198D
If the data for an MCR operation is not available inside the ARM9EJ-S core pipeline
during its first Decode cycle, then the ARM9EJ-S core pipeline interlocks for one or
more cycles until the data is available. An example of this is where the register being
transferred is the destination from a preceding LDR instruction. In this situation the
MCR instruction enters the Decode stage of the coprocessor pipeline, and remains there
for a number of cycles before entering the Execute stage.
Figure 8-5 shows an example of an interlocked MCR.
Fetch
Decode
(interlock)
MCR/MRC
WAIT
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Decode
Execute
Execute
(WAIT)
WAIT
LAST
Coprocessor Interface
Memory
(LAST)
Ignored
Coproc data

Figure 8-5 Interlocked MCR

Write
8-7