Tcm Interface Examples; Figure 5-12 Zero Wait State Ram Example - ARM ARM926EJ-S Technical Reference Manual

Tightly-Coupled Memory Interface
5.5

TCM interface examples

5.5.1 Zero-wait-state RAM example
5.5.2 Producing byte writable memory using word writable RAM
5-20
This section contains the following examples:
• Zero-wait-state RAM example
• Producing byte writable memory using word writable RAM
• Multiple banks of RAM example on page 5-21.
Note
Most of the examples in this section are for the DTCM interface. These are also
applicable to the ITCM interface.
The additional logic required for implementing the examples in this section is the
responsibility of the implementer.
Figure 5-12 shows the simplest RAM interface where the RAM block is constructed
from a single word-wide RAM that has byte write control. The TCM interface can
connect directly to the RAM block. This is a zero-wait-state memory so DRWAIT is
tied LOW.
If byte-write RAM is not available, four banks of byte-wide RAM must be used as
shown in Figure 5-13 on page 5-21.
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM926EJ-S
DRSIZE[3:0] b0110
[14:0]
DRADDR[17:0]
DRWD[31:0]
DRnRW
DRWBL[3:0]
DRCS
DRRD[31:0]
DRIDLE
DRSEQ
DRWAIT

Figure 5-12 Zero wait state RAM example

RAM 32KB
CLK CLK
A[14:0]
DIN[31:0]
nRW
BW[3:0]
CS
DOUT[31:0]
ARM DDI0198D