ARM ARM926EJ-S Technical Reference Manual page 248

Index
Stall cycles 5-29, 5-30
Status field 2-19
Subpages 3-20
Synchronizing data and instruction
streams 9-3
System control coprocessor registers
2-3
System protection 2-14
T
TCM
access priorities 4-8
optimizing for power 5-22
optimizing for speed 5-23
region register 2-26
region register, using 5-19
status register 2-7, 2-12
TCM interface
examples 5-20
signals A-14
TCM status register 2-7
Test and clean
DCache 2-21
operations 2-24
Test and debug register 2-36
Test registers B-2
Test, clean, and invalidate DCache
2-21
Thumb instruction fetches 6-6
Timing diagram conventions xviii
Tiny page references, translating 3-19
TLB
lockdown register 2-32
operations 2-25
structure 3-31
TLB operations register 2-24
Trace control register B-5
Trace port 10-2
Transfer size 6-3
Translated entries 3-3
Translating page tables 3-7
Translation fault 3-27
Translation table base 3-6
register 2-17
Trigering facilities 10-2
TTB 3-6
Typographical conventions xviii
Index-4
U
UND 2-5
Undefined 2-5
Unified or separate cache 2-9
Unlock procedure 2-29
UNP 2-5
Unpredictable 2-5
V
V bit 2-14
VA 2-4
Victim field 2-32
Virtual address 2-4
W
Wait for interrupt 2-22
Wait for interrupt mode 12-2
Write buffer 4-4
Writeback (WB)
C and B bits 4-2
caches 4-2
Write-through (WT)
C and B bits 4-2
cache operation 4-2
caches 4-2
Z
Zero-wait-state RAM 5-20
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