Address Translation; Figure 3-5 Section Descriptor - ARM ARM926EJ-S Technical Reference Manual

3.2

Address translation

ARM DDI0198D
The VA generated by the CPU core is converted to a Modified Virtual Address (MVA)
by the FCSE using the value held in CP15 c13. The MMU translates MVAs into
physical addresses to access external memory, and also performs access permission
checking.
The MMU table-walking hardware is used to add entries to the TLB. The translation
information that comprises both the address translation data and the access permission
data resides in a translation table located in physical memory. The MMU provides the
logic for automatically traversing this translation table and loading entries into the TLB.
The number of stages in the hardware table walking and permission checking process
is one or two depending on whether the address is marked as a section-mapped access
or a page-mapped access.
There are three sizes of page-mapped accesses and one size of section-mapped access.
Page-mapped accesses are for:
• large pages
• small pages
• tiny pages.
The translation process always begins in the same way, with a level one fetch. A
section-mapped access requires only a level one fetch, but a page-mapped access
requires an additional level two fetch.
The following subsections are:
• Translation table base on page 3-6
• First-level fetch on page 3-8
• First-level descriptor on page 3-8
• Section descriptor on page 3-10
• Coarse page table descriptor on page 3-11
• Fine page table descriptor on page 3-12
• Translating section references on page 3-13
• Second-level descriptor on page 3-14
• Translating large page references on page 3-16
• Translating small page references on page 3-18
• Translating tiny page references on page 3-19.
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Memory Management Unit
3-5