Figure 5-6 Generating A Single Wait State For Itcm Accesses Using Irwait - ARM ARM926EJ-S Technical Reference Manual

5.3.3 Multi-cycle access timing
ARM DDI0198D
If non zero wait state memory is used for TCM, then the DRWAIT/IRWAIT signals
are used to wait the ARM926EJ-S. The wait information for a data cycle is pipelined so
that the value of DRWAIT/IRWAIT pertains to the following data cycle, which
corresponds to the request cycle for the first data cycle. If there is no active TCM access
then the value on DRWAIT/IRWAIT is ignored. This allows the wait signals to be
generated speculatively.
Figure 5-6 shows how the speculative generation of IRWAIT can be used to generate a
single wait state for every ITCM access.
T1
CLK
IRCS
IRWAIT
IRADDR
IRRD

Figure 5-6 Generating a single wait state for ITCM accesses using IRWAIT

In cycle T1, IRWAIT is asserted but no request is made.
In cycle T2, IRWAIT is asserted and a request is made.
In cycle T3, IRWAIT is deasserted indicating that the access to A will complete in the
following cycle.
In cycle T4, IRWAIT is asserted and a request is made. The access to A completes.
In cycle T5, IRWAIT is deasserted indicating that the access to B will complete in the
following cycle.
In cycle T6, IRWAIT is asserted. No request is made. The access to B completes.
The logic required for the above example corresponds to the two-state state machine
shown in Figure 5-7 on page 5-14.
Copyright © 2001-2003 ARM Limited. All rights reserved.
T2 T3 T4
A
Tightly-Coupled Memory Interface
T5 T6
B
I(A) I(B)
5-13