Figure 2-6 Ttbr Format - ARM ARM926EJ-S Technical Reference Manual

2.3.3 Translation Table Base Register c2
31
2.3.4 Domain Access Control Register c3
ARM DDI0198D
Note
Read accesses on the TCM interface are not prevented when an ARM9EJ-S core
memory access is aborted. All reads on the TCM interface must be treated as
speculative. ARM92EJ-S processor write accesses that are aborted do not take place on
the TCM interface.
Register c2 is the Translation Table Base Register (TTBR), for the base address of the
first-level translation table.
Reading from c2 returns the pointer to the currently active first-level translation table in
bits [31:14] and an Unpredictable value in bits [13:0].
Writing to register c2 updates the pointer to the first-level translation table from the
value in bits [31:14] of the written value. Bits [13:0] Should Be Zero.
You can use the following instructions to access the TTBR:
MRC p15, 0, <Rd>, c2, c0, 0; read TTBR
MCR p15, 0, <Rd>, c2, c0, 0; write TTBR
The CRm and Opcode_2 fields Should Be Zero when writing to c2.
Figure 2-6 shows the format of the Translation Table Base Register.
Translation table base
Register c3 is the Domain Access Control Register consisting of 16 two-bit fields as
shown in Figure 2-7 on page 2-18.
Copyright © 2001-2003 ARM Limited. All rights reserved.
14 13
UNP/SBZ

Figure 2-6 TTBR format

Programmer's Model
0
2-17