Cpabort; Figure 8-9 Cpburst And Cpabort Timing - ARM ARM926EJ-S Technical Reference Manual

Coprocessor Interface
8.8

CPABORT

Coprocessor pipeline
8-12
The CPABORT signal being asserted HIGH indicates that an
aborted. CPABORT is asserted in the cycle after the Memory stage of the aborting
LDC/STC instruction. This is shown in Figure 8-9.
Fetch
CLK
CPINSTR[31:0]
LDC/STC
nCPMREQ
CHSDE[1:0]
CHSEX[1:0]
0000
CPBURST
CPDIN[3:0]
CPDOUT[3:0]
CPABORT
Copyright © 2001-2003 ARM Limited. All rights reserved.
Execute 2
Execute 1 Memory 1
Decode
GO ABSENT
ABSENT LAST
0001 0000

Figure 8-9 CPBURST and CPABORT timing

/ instruction has
LDC STC
Memory 2 Write 2
Write 1
ARM DDI0198D