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3.2.13 Exception Program Counter (EPC) register (14)
The Exception Program Counter (EPC) is a read/write register that contains the address at which processing
resumes after an exception has been serviced.
execution of MIPS16 instructions is enabled or disabled. Setting the MIPS16EN pin after RTC reset specifies
whether execution of the MIPS16 instructions is enabled or disabled.
When the MIPS16 instruction execution is disabled, either of the following addresses is contained in the EPC
register:
• Virtual address of the instruction that caused the exception
• Virtual address of the immediately preceding branch or jump instruction (when the instruction associated with
the exception is in a branch delay slot, and the BD bit in the Cause register is set to 1)
When the MIPS16 instruction execution is enabled, either of the following addresses is contained in the EPC
register during a 32-bit instruction execution:
• Virtual address of the instruction that caused the exception and ISA mode at which an exception occurs
• Virtual address of the immediately preceding branch or jump instruction and ISA mode at which an exception
occurs (when the instruction associated with the exception is in a branch delay slot of the jump instruction, and
the BD bit in the Cause register is set to 1)
When the 16-bit instruction is executed, either of the following addresses is contained in the EPC register:
• Virtual address of the instruction that caused the exception and ISA mode at which an exception occurs
• Virtual address of the immediately preceding Extend or jump instruction and ISA mode at which an exception
occurs (when the instruction associated with the exception is in a branch delay slot of the jump instruction or in
the instruction following the Extend instruction, and the BD bit in the Cause register is set to 1)
The EXL bit in the Status register is set to 1 to keep the processor from overwriting the address of the exception-
causing instruction contained in the EPC register in the event of another exception.
The EPC register never indicates the address of the instruction in a branch delay slot.
31
63
EPC:
Restart address (virtual) after exception processing.
CHAPTER 3 CP0 REGISTERS
The contents of this register change depending on whether
Figure 3-15. EPC Register (When MIPS16 ISA Is Disabled)
(a) 32-bit mode
(b) 64-bit mode
User's Manual U14272EJ3V0UM
EPC
EPC
0
0
81
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