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Exception code
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1
2
3
4
5
6
7
8
9
10
11
12
13
14 to 22
23
24 to 31
The V
4181 has eight interrupt request sources, IP7 to IP0. They are used for the purpose as follows.
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For the detailed description of interrupts of the CPU core, refer to V
(1) IP7
This bit indicates whether there is a timer interrupt request.
It is set when the values of the Count register and Compare register match.
(2) IP6 to IP2
IP6 to IP2 reflect the state of the interrupt request signals of the CPU core.
(3) IP1 and IP0
These bits are used to set/clear a software interrupt request.
80
CHAPTER 3 CP0 REGISTERS
Table 3-4. Cause Register Exception Code Field
Mnemonic
Int
Interrupt exception
Mod
TLB Modified exception
TLBL
TLB Refill exception (load or fetch)
TLBS
TLB Refill exception (store)
AdEL
Address Error exception (load or fetch)
AdES
Address Error exception (store)
IBE
Bus Error exception (instruction fetch)
DBE
Bus Error exception (data load or store)
Sys
System Call exception
Bp
Breakpoint exception
RI
Reserved Instruction exception
CpU
Coprocessor Unusable exception
Ov
Integer Overflow exception
Tr
Trap exception
Reserved for future use
WATCH
Watch exception
Reserved for future use
User's Manual U14272EJ3V0UM
Description
4100 Series Architecture User's Manual.
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