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3.2.22 ErrorEPC register (30)
The Error Exception Program Counter (ErrorEPC) register is similar to the EPC register. It is used to store the
Program Counter value at which the Cold Reset, Soft Reset, or NMI exception has been serviced.
The read/write ErrorEPC register contains the virtual address at which instruction processing can resume after
servicing an error. The contents of this register change depending on whether execution of MIPS16 instructions is
enabled or disabled.
Setting the MIPS16EN pin after RTC reset specifies whether the execution of MIPS16
instructions is enabled or disabled.
When the MIPS16 instruction execution is disabled, either of the following addresses is contained in the ErrorEPC
register:
• Virtual address of the instruction that caused the exception
• Virtual address of the immediately preceding branch or jump instruction, when the instruction associated with
the error exception is in a branch delay slot, and the BD bit in the Cause register is set to 1
When the MIPS16 instruction execution is enabled, either of the following addresses is contained in the ErrorEPC
register during a 32-bit instruction execution:
• Virtual address of the instruction that caused the exception and ISA mode at which an exception occurs
• Virtual address of the immediately preceding branch or jump instruction and ISA mode at which an exception
occurs when the instruction associated with the error exception is in a branch delay slot, and the BD bit in the
Cause register is set to 1
When the 16-bit instruction is executed, either of the following addresses is contained in the ErrorEPC register:
• Virtual address of the instruction that caused the exception and ISA mode at which an exception occurs
• Virtual address of the immediately preceding jump instruction or Extend instruction and ISA mode at which an
exception occurs when the instruction associated with the error exception is in a branch delay slot of the jump
instruction or is the instruction following the Extend instruction, and the BD bit in the Cause register is set to 1
The contents of the ErrorEPC register do not change when the ERL bit of the Status register is set to 1. This
prevents the processor when other exceptions occur from overwriting the address of the instruction in this register
that causes an error exception.
The ErrorEPC register never indicates the address of the instruction in a branch delay slot.
CHAPTER 3 CP0 REGISTERS
User's Manual U14272EJ3V0UM
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