Gphibsth (0X0B00 0316) - NEC VR4181 mPD30181 User Manual

13.3.12 GPHIBSTH (0x0B00 0316)

Bit 15
Name GPHST31
R/W R/W
RTCRST 0
Note
Other resets
Bit 7
Name GPHST23
R/W R/W
RTCRST 0
Other resets Note
Bit Name
15 to 0 GPHST(31:16)
Note Holds the value before reset
Caution GPIO29 pin (DCD1#) can be input at high level and monitored during Hibernate mode and
therefore the GPHST29 bit can be set to 1. The GPHST bits for all other GPIO pins configured as
inputs should be reset to 0.
CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU)
14 13
GPHST30 GPHST29 GPHST28
R/W R/W
0 0
Note Note
6 5
GPHST22 GPHST21 GPHST20
R/W R/W
0 0
Note Note
GPIO Hibernate pin state control. There is a one-to-one correspondence between
these bits and GPIO pins. These bits determine the state of GPIO(31:16) pins
during Hibernate mode as follows:
0 : Output pin is in high impedance
Input pin is ignored during Hibernate mode
1 : Output pin remains actively driven
Input pin is monitored during Hibernate mode
User's Manual U14272EJ3V0UM
12 11 10
GPHST27 GPHST26
R/W R/W R/W
0 0
Note Note Note
4 3
GPHST19 GPHST18
R/W R/W R/W
0 0
Note Note Note
Function
9 8
GPHST25 GPHST24
R/W R/W
0 0 0
Note Note
2 1 0
GPHST17 GPHST16
R/W R/W
0 0 0
Note Note
263