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Bit
Name
2
HALTIMERRST
1
Reserved
0
Reserved
Notes1. When the HALTIMERRST bit is cleared to 0 just after set to 1, the HALTimer may not be reset. Wait more
than 6 RTC clock cycles from writing 1 to writing 0.
2. Verify that the HALTIMERRST bit is 0 before reset the HALTimer. When this bit is 1, the HALTimer is not
reset even if write 1 to this bit. In this case, write 0 to this bit first, then write 1 after more than 6 RTC clock
cycles.
This register is used to set CPU core shutdown and overall system operations management.
The HALTIMERRST bit must be reset within about four seconds after activation. Resetting of the HALTIMERRST
bit indicates that the V
4181 itself has been activated normally. If the HALTIMERRST bit is not reset within about four
R
seconds after activation, program execution is regarded as abnormal (possibly due to a runaway) and an automatic
shutdown is performed.
212
CHAPTER 10 POWER MANAGEMENT UNIT (PMU)
HALTimer reset
1 : Reset
0 : Set
This bit is cleared to 0 automatically after reset of the HALTimer
0 is returned when read
Write 0 when write. 0 is returned when read.
User's Manual U14272EJ3V0UM
Function
Note1, 2
(2/2)
.
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