Memory Controller Register Set; Edomcytreg (0X0A00 0300) - NEC VR4181 mPD30181 User Manual

6.5 Memory Controller Register Set

Physical address R/W
0x0A00 0300 R/W
0x0A00 0304 R/W
0x0A00 0308 R/W
0x0A00 030C R/W
Caution Since these registers are powered by 2.5 V power supply, the contents of these registers are
cleared after Hibernate mode.

6.5.1 EDOMCYTREG (0x0A00 0300)

Bit 15
Name Reserved
R/W R
At reset 0
Bit 7
Name Rcasdly1
R/W R/W
At reset 0
Bit Name
15 to 13 Reserved
12 to 10 SrefRpre(2:0)
9, 8 Caspre(1:0)
7, 6 Rcasdly(1:0)
CHAPTER 6 BUS CONTROL
Table 6-3. Memory Controller Registers
Register symbol
EDOMCYTREG
MEMCFG_REG
MODE_REG
SDTIMINGREG
14 13
Reserved Reserved SrefRpre2
R R
0 0
6 5
Rcasdly0 Tcas1
R/W R/W
0 0
0 is returned when read
Self refresh RAS precharge time
000 : 3 TClock
001 : 4 TClock
010 : 6 TClock
011 : 8 TClock
100 : 11 TClock
Others : Reserved
CAS precharge time
00 : 1/2 TClock
01 : 1 TClock
10 : 2 TClock
11 : Reserved
RAS to CAS delay time
00 : 2 TClock
01 : 3 TClock
10 : 5 TClock
11 : 6 TClock
User's Manual U14272EJ3V0UM
EDO DRAM timing register
Memory configuration register
SDRAM mode register
SDRAM timing register
12 11
SrefRpre1 SrefRpre0
R/W R/W
0 0
4 3
Tcas0 Trp1
R/W R/W
0 0
Function
Function
10 9
Caspre1 Caspre0
R/W R/W R/W
0 0
2 1
Trp0 Tras1 Tras0
R/W R/W R/W
0 0
(1/2)
8
0
0
0
131