Bcurfcntreg (0X0A00 0010) - NEC VR4181 mPD30181 User Manual

6.2.4 BCURFCNTREG (0x0A00 0010)

Bit 15
Name Reserved
R/W R
At reset 0
Bit 7
Name BRF7
R/W R/W
At reset 1
Bit Name
15, 14 Reserved
13 to 0 BRF(13:0)
Remarks 1. When the IORDY signal does not become high level though the DRAM refresh rate has elapsed
during the external ISA memory or I/O cycles, a DRAM refresh cycle may be lost.
2. Refresh timing is generated from detecting match between values of the internal up counter and
BCURFCNTREG register. Therefore, when the BCURFCNTREG register value is changed smaller
than current value, and if the internal counter value is larger than the new BCURFCNTREG register
value, the next CBR refresh timing is at next match after the counter rounds over.
CHAPTER 6 BUS CONTROL
14 13
Reserved BRF13
R R/W
0 0
6 5
BRF6 BRF5
R/W R/W
1 1
0 is returned when read
These bits select the DRAM refresh rate that is based on the TClock. The refresh
rate is obtained by following expression.
Refresh rate = BRF(13:0) x TClock period
For example, to select a 15.6 µ s refresh rate with a 50 MHz TClock:
BRF(13:0) = 15600 (ns) / 20 (ns) = 0x30C
User's Manual U14272EJ3V0UM
12 11
BRF12 BRF11 BRF10
R/W R/W
1 1
4 3
BRF4 BRF3
R/W R/W
1 1
Function
10 9
BRF9 BRF8
R/W R/W
1 1
2 1
BRF2 BRF1 BRF0
R/W R/W
1 1
8
R/W
1
0
R/W
1
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