Fbendadreg1 (0X0A00 0420); Fbendadreg2 (0X0A00 0422) - NEC VR4181 mPD30181 User Manual

21.4.15 FBENDADREG1 (0x0A00 0420)

Bit 15
Name FBEA15
R/W R/W
Reset 0
Bit 7
Name FBEA7
R/W R/W
Reset 0
Bit Name
15 to 0 FBEA(15:0)

21.4.16 FBENDADREG2 (0x0A00 0422)

Bit 15
Name FBEA31
R/W R
Reset 0
Bit 7
Name FBEA23
R/W R/W
Reset 0
Bit Name
15 to 0 FBEA(31:16)
CHAPTER 21 LCD CONTROLLER
14 13
FBEA14 FBEA13 FBEA12
R/W R/W
0 0
6 5
FBEA6 FBEA5
R/W R/W
0 0
Frame buffer end address (lower 16 bits)
14 13
FBEA30 FBEA29 FBEA28
R R
0 0
6 5
FBEA22 FBEA21 FBEA20
R/W R/W
0 0
Frame buffer end address (upper 16 bits)
FBEA(31:29) are always 0 when read.
User's Manual U14272EJ3V0UM
12 11
FBEA11 FBEA10
R/W R/W
0 0
4 3
FBEA4 FBEA3 FBEA2
R/W R/W
0 0
Function
12 11
FBEA27 FBEA26
R/W R/W
0 0
4 3
FBEA19 FBEA18
R/W R/W
0 0
Function
10 9
FBEA9 FBEA8
R/W R/W R/W
0 0
2 1
FBEA1 FBEA0
R/W R/W R/W
0 0
10 9
FBEA25 FBEA24
R/W R/W R/W
0 0
2 1
FBEA17 FBEA16
R/W R/W R/W
0 0
8
0
0
0
8
0
0
0
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