Xisactl (0X0B00 02C4) - NEC VR4181 mPD30181 User Manual

6.7.3 XISACTL (0x0B00 02C4)

Bit 15
Name Reserved
R/W R
RTCRST 0
Other resets 0
Bit 7
Name MEMWS1
R/W R/W
RTCRST 0
Other resets 0
Bit Name
15 to 11 Reserved
10 EXTRESULT
9 INTRESULT
8 EXBUFFEN
7, 6 MEMWS(1:0)
5, 4 IOWS(1:0)
140
CHAPTER 6 BUS CONTROL
14 13
Reserved Reserved Reserved
R R
0 0
0 0
6 5
MEMWS0 IOWS1
R/W R/W
0 0
0 0
0 is returned when read
External ISA result cycle enable
0 : Disabled. The MBA bus arbiter waits until an external ISA read is finished.
1 : Enabled. The MBA bus arbiter issues a result cycle to the ISA bridge after
finishing an external ISA cycle and obtains results of the read.
Normally, set 1 to this bit.
Internal ISA result cycle enable
0 : Disabled. The MBA bus arbiter waits until an internal ISA read is finished.
1 : Enabled. The MBA bus arbiter issues a result cycle to the ISA bridge after
finishing an internal ISA cycle and obtains results of the read.
Normally, set 1 to this bit.
External buffer enable
0 : Enable external buffer control with SYSDIR and SYSEN# pins
1 : Disable external buffer control with SYSDIR and SYSEN# pins
(SYSEN# and SYSDIR pins are both forced to low level)
External ISA memory wait states (read/write strobe width)
00 : 1.5 SYSCLK cycles
01 : 2.5 SYSCLK cycles
10 : 3.5 SYSCLK cycles
11 : 4.5 SYSCLK cycles
External ISA I/O wait states (read/write strobe width)
00 : 1.5 SYSCLK cycles
01 : 2.5 SYSCLK cycles
10 : 3.5 SYSCLK cycles
11 : 4.5 SYSCLK cycles
User's Manual U14272EJ3V0UM
12 11
EXTRESULT
Reserved
R R
0 0
0 0
4 3
IOWS0 Reserved Reserved
R/W R
0 0
0 0
Function
10 9
INTRESULT EXBUFFEN
R/W R/W R/W
1 0
1 0
2 1
SCLKDIV1 SCLKDIV0
R R/W R/W
0 0
0 0
(1/2)
8
1
1
0
0
0