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9.1 Overview
The ICU collects interrupt requests from the various on-chip peripheral units and transfers them with internal
interrupt request signals (Int0, Int1, Int2, Int3, Int4, and NMI) to the CPU core.
The signals used to notice interrupt requests to the CPU are as below.
NMI: battint only. However, the signal for battint can be switched between NMI and Int0 is enabled according
to NMIREG register's settings. Because NMI's interrupt masking cannot be controlled by means of
software, switch to Int0 to mask battint.
Int4: Not used (fixed to 1 (inactive))
Int3: Not used (fixed to 1 (inactive))
Int2: rtclong2 only (RTCLong2 Timer)
Int1: rtclong1 only (RTCLong1 Timer)
Int0: All other interrupts.
For details of the interrupt sources, see 9.2 Register Set.
How an interrupt request is notified to the CPU core is shown below.
If an interrupt request occurs in the peripheral units, the corresponding bit in the interrupt indication register of
Level 2 (xxxINTREG) is set to 1. The interrupt indication register is ANDed bit-wise with the corresponding interrupt
mask register of Level 2 (MxxxINTREG). If the occurred interrupt request is enabled (set to 1) in the mask register,
the interrupt request is notified to the interrupt indication register of Level 1 (SYSINTREG) and the corresponding bit
is set to 1. At this time, the interrupt requests from the same register of Level 2 are notified to the SYSINTREG as a
single interrupt request.
Interrupt requests from some units directly set their corresponding bits in the SYSINTREG.
The SYSINTREG is ANDed bit-wise with the interrupt mask register of Level 1 (MSYSINTREG). If the interrupt
request is enabled (set to 1) in the MSYSINTREG, a corresponding interrupt request signal is output from the ICU to
the CPU core. battintr is connected to the NMI or Int0 signal of the CPU core (selected by setting of NMIREG).
rtclong2 and rtclong1 signals are connected to the Int2 or Int1 signal of the CPU core. The other interrupt requests
are connected to the Int0 signal of the CPU core as a single interrupt request.
The following figure shows an outline of interrupt control in the ICU.
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU)
User's Manual U14272EJ3V0UM
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